1. Field of the Invention
Telephone circuits and VOIP (voice over Internet protocol) ATAs (analog terminal adapters) as applied in analog telephone line circuits that interface through a 2 wire connection with a characteristic termination impedance within the voice band (200 Hz, 3400 Hz).
2. Prior Art
Throughout the global telephony administrations, three types of characteristic telephone line impedances ZL can be found. These are shown in the three cases of FIG. 1.
Examples of actual values applicable to FIG. 1 are shown in Table 1.
TABLE 1R1R2C1(Ohm)(Ohm)(Farad)1US PBX, Korea, Taiwan600002Brazil900003Japan CO60001.00E−064Bellcore90002.16E−065CTR212707501.50E−076China CO2006801.00E−077China PBX2005601.00E−078Japan PBX10010001.00E−079India, New Zealand3706203.10E−0710Germany2208201.15E−0711UK32010502.30E−0712Australia2208201.20E−07
In addition, the impedance at 12 kHz or 16 kHz is defined at certain administrations when Teletax (metering pulse) is in use. Generally, a fixed resistance of 200 Ohm is used in that case.
The impedance matching is measured by means of the 2 Wire Return Loss RL2W, which is a measure of the amount of reflection R on the telephone line. It can be calculated by:
      RL          2      ⁢      W        =                    -        20            ·                        log          10                ⁡                  (          R          )                      =                            -          20                ·                  log          10                    ⁢                                                          Z              L                        -                          Z              S                                                          Z              L                        +                          Z              S                                                  
where ZL is the telephone line impedance and ZS is the source impedance.
In the ideal case, the return loss is infinite, but when ZL and ZS are not exactly matched, reflection will occur and the return loss can be calculated. The return loss can be measured directly on a 2 Wire connection.
Another way to look at the return loss is through the trans hybrid return loss TBRL. This also includes the Hybrid Balance Gain AHB.
      TBRL    =                            -          20                ·                  log          10                    ⁢                                                                          (                                  2                  -                                      2                    ·                                          A                      HB                                                                      )                            ·                              Z                L                                      -                          2              ·                              A                HB                            ·                              Z                S                                                                        Z              L                        +                          Z              S                                                        TBRL    ⁢                                    AHB          =          0.5                    ⁢              =                                                            -                20                            ·                              log                10                                      ⁢                                                                                              Z                    L                                    -                                      Z                    S                                                                                        Z                    L                                    +                                      Z                    S                                                                                      ⁢                                                  ⁢                          A              HB                                =          HybridBalanceGain                    
At the ideal hybrid balance, the equation resolves into the same equation as the 2 Wire return Loss. The trans hybrid return loss can be measured at the switching side of the network.
Impedance matching circuits in POTS (plain old telephone system) telephone line circuits have been used since full duplex 2 wire connections were in place. The early solutions used expensive and bulky transformers with multi-taps. Later, more advanced solid-state solutions using amplifiers and external discretes were used. Examples of this arrangement can be found in U.S. Pat. Nos. 4,789,999, 4,631,359 and 5,402,485. These solutions were non-programmable and required replacement of matching components at the application level.
FIG. 2 illustrates the typical arrangement of a prior art solid-state impedance matching circuit, such as shown in U.S. Pat. No. 4,789,999. The impedance matching circuit in combination with the feedback loop synthesizes a termination impedance as well as a source impedance ZS, which matches the characteristic telephone line impedance ZL. The telephone line is terminated by a telephone or other telecom product having the same characteristic termination impedance and a voltage source to transmit voice data to the Tx ADC path. The equivalent circuit block diagram then looks like FIG. 3.
Existing solutions of an integrated programmable termination and source impedance for a telephone line interface circuit (SLIC) are described in U.S. Pat. Nos. 6,925,171 and 6,735,302. In these inventions, the impedance matching circuit is implemented by a continuous time path in parallel with a complex digital filter. These digital filters require a DAC, an ADC, anti-aliasing and smoothing filters to operate. This will cause a time delay of the in-band signals. The delay will have a limitation on the maximum possible return loss or trans hybrid return loss. This can be explained by taking two cosine wave signals and subtracting them, which is generally done inside the hybrid balancing circuit shown in FIGS. 2 and 3. Considering the impedance matching circuit to be ideal, apart from having a delay τD due to the ADC/DAC conversion and filtering, the voltages V1 and V2 can be described as:
            V      ⁢                          ⁢      1        =          A      ·              cos        ⁡                  (                      ω            ·                          (                              t                +                                                      τ                    ⁢                                                                                  ⁢                    D                                    2                                            )                                )                                V      ⁢                          ⁢      2        =          A      ·              cos        ⁡                  (                      ω            ·                          (                              t                -                                                      τ                    ⁢                                                                                  ⁢                    D                                    2                                            )                                )                                Using      ⁢              :            ⁢                          ⁢      cos      ⁢                          ⁢              α        ·        cos            ⁢                          ⁢      β        =                            1          2                ·                  cos          ⁡                      (                          α              -              β                        )                              +                        1          2                ·                  cos          ⁡                      (                          α              +              β                        )                                                  V        ⁢                                  ⁢        1            -              V        ⁢                                  ⁢        2              =          2      ·      A      ·              sin        ⁡                  (                      ω            ·            t                    )                    ·              sin        ⁡                  (                                    ω              ·              τ                        ⁢                                                  ⁢            D                    )                    
The maximum achievable trans hybrid return loss for this example would be:V1−V2=20·Log10(2·sin(ω·τD))ω=2·n·frequency
Examples of this are illustrated in FIG. 4. As shown, the delay limits the return loss at higher frequencies, which is also shown in U.S. Pat. No. 6,925,171. A compensation filter can be added to compensate for this delay. This is shown in U.S. Pat. No. 6,920,471.
Another approach of solid state impedance matching is shown in U.S. Pat. No. 4,558,185. In this approach, a switched capacitor network is used for the impedance matching filter. This filter requires an anti-aliasing filter and smoothing filter in order to suppress clock noise on the telephone line. Also, there is no continuous time feedback path available. Therefore, this approach also has limited performance due to group delay.